Power MOS devices are commonly used in electronic circuits. Depending on the application, different device characteristics may be desirable. One common application is a DC-DC converter, which includes a power MOS device as a synchronous rectifier (also referred to as the low side FET) and another power MOS device as a control switch (also referred to as the high side FET). The low side FET typically requires a small on-resistance to achieve good power switch efficiency. The high side FET typically requires a small gate capacitance for fast switching and good performance.
The value of a transistor's on-resistance (Rdson) is typically proportional to the channel length (L) and inversely proportional to the number of active cells per unit area (W). To reduce the value of Rdson, the channel length can be reduced by using shallower source and body, and the number of cells per unit area can be increased by reducing the cell size. However, the channel length L is typically limited because of the punch-through phenomenon. The number of cells per unit area is limited by manufacturing technology and by the need to make a good contact to both the source and body regions of the cell. As the channel length and the cell density increase, the gate capacitance increases. Lower device capacitance is preferred for reduced switching losses. In some applications such as synchronous rectification, the stored charge and forward drop of the body diode also result in efficiency loss. These factors together tend to limit the performance of DMOS power devices.
It would be desirable if the on-resistance and the gate capacitance of DMOS power devices could be reduced from the levels currently achievable, so that the reliability and power consumption of the power switch could be improved. It would also be useful to develop a practical process that could reliably manufacture the improved DMOS power devices.